1. Field of the Invention
The prevent invention relates to charge pump circuit, more particularly, to method and apparatus for canceling mismatch and suppressing clock feedthrough for charge pump circuit.
2. Description of Related Art
A typical PLL (phase lock loop) comprises a PFD (phase/frequency detector), a charge pump circuit, a loop filter, and a VCO (voltage controlled oscillator). The PFD compares the phase of a reference clock with that of the output clock of the VCO. Usually two logical signals, said UP and DN signals are used by the PFD to represent the phase difference between the two clocks. Each time a phase comparison is made, an UP pulse and a DN pulse are generated. If the reference clock is leading the VCO output clock (in clock phase), the UP pulse is longer than the DN pulse. Otherwise, the DN pulse is longer than the UP pulse. The two logical signals are converted into a current signal using the charge pump circuit. FIG. 1 schematically depicts a prior art charge pump circuit. Throughout this disclosure, VDD denotes a supply voltage. The charge pump circuit comprises a current source 110 of magnitude I, a switch 120 controlled by the UP signal, a current sink 130 of magnitude I, and a switch 140 controlled by the DN signal. When UP is 1 and DN is 0, the output current IOUT is positive (i.e. out-flowing). When UP is 0 and DN is 1, the output current IOUT is negative (i.e. in-flowing). When UP is 0 and DN is 0, the output current IOUT is zero. The output of the charge pump is coupled to the loop filter, which typically comprises a resistor in series with a capacitor to convert the output current from the charge pump into a voltage, which is used to control the VCO.
In practice, however, the prior art charge pump circuits shown in FIG. 1 are prone to problems due to circuit non-idealities. First, the magnitude of the current source 110 may not be exactly the same as that of the current sink 130 due to variation within the manufacturing process. Second, the switching activities of switch 120 and 140 will induce noises such as feedthrough and charge injection, resulting in voltage ripple on node IOUT. These non-idealities will lead to performance degradation to the PLL. To be specific, they lead to clock jitters in a periodic fashion, which in frequency domain appear as a plurality of spurious spectral components. In particular, the strongest spurious spectral component, known as the reference spur, appears at a frequency location that is exactly the same as the reference clock frequency.
The conventional method disclosed by Wakayama (in U.S. Pat. No. 6,326,852) has a few drawbacks. First, the circuit complexity is high. Second, the offset voltage of the operational amplifier will degrade the accuracy of the cancellation. Third, it can at best alleviate the UP/DN current mismatch but still cannot solve the aforementioned problem of the noises induced due to the switching activities of switches.
What is needed is a low-complexity method to remove the UP/DN current mismatch and also alleviate the problem of the noises induced due to the switching activities.